Software-defined networking (SDN) technology allows for fast and easy adaptation of a network to new standards, protocols and services. SDN separates the network abstract into two separate planes: a control plane and a data transfer plane. This separation allows network operators to quickly change features of and/or add new features to the network by configuring/programming the control plane while reusing the expensive existing data transfer plane. SDN is able to reduce cost and time in deploying new network features and services. The plane-separated networking infrastructure is also able to simplify management tasks for network operators.
Each SDN device is often required to process multiple high-throughput data flows in parallel. In such a SDN device, there are one or more processing engines which are responsible for manipulating the data. Data manipulation in these processing engines depends on the data's contents themselves and the network features which are configured for the SDN device. The data processed by these processing engines can be in large sizes which can be up to hundreds of bytes each.
The prior art ASIC-based designs do not provide enough flexibility for reprogramming and/or reconfiguring to perform different network features as expected in a SDN processing engine. Otherwise, using state-of-the-art 64-bit general-purpose CPUs for implementing these engines cannot satisfy the network bandwidth and latency requirement of SDN devices which are required to process hundreds of data bytes per cycle. Other prior art implementations using FPGAs are also not appropriate for performing complex network protocols at high throughput due to their limitations in logic cell capacity and the high complexity in their internal interconnect wirings which make FPGA chips running at low frequency with high latency.